It remains a continuing goal of integrated circuits and electronic systems to provide rapid communication between devices. At the same time, it is desirable that communication signals maintain a certain degree of integrity. As data transmission speeds increase, transmission line effects, and the like can affect signal quality.
As is well known, various forms of signal termination can address transmission line effects and thus improve signal integrity. For example, some circuit boards can include termination resistors to match a predetermined characteristic impedance of a signal line, or otherwise reduce signal reflection. A drawback to such approaches can be the increased component count in a resulting circuit board. This can increase overall device cost and/or size.
Conventionally, one approach to addressing the above drawback can be to include termination impedance on an integrated circuit device itself. Such on-die-termination (ODT) can eliminate the need for external board termination devices.
An input circuit of an integrated circuit device typically includes a compare circuit that compares a signal potential/current to some other value. While some approaches can include differential compare circuits that receive complementary signals, such approaches are undesirable as two signal lines are required per input value. To reduce signal line count, input circuits can be “single ended referential inputs.” Single ended referential input circuits can receive an input signal on one signal line, and compare the voltage/current of the input signal to a corresponding reference voltage/current. In many cases, the reference voltage/current can be generated “on-chip” (e.g., on the integrated circuit device).
One example of a conventional single ended referential input circuit is set forth in FIG. 7A and designated by the general reference character 700. FIG. 7A shows an input circuit with a conventional comparator arrangement. In particular, differences in potential between an input signal IN and a reference voltage REF are detected by differential transistor pair N70 and N71. Such a difference is amplified by a differential amplifier stage that includes differential pair N73 and N74 and current mirror P70/P71. It is understood that the conventional circuit of FIG. 7A could be subject to some variation. While the input stage shown is an NMOS type input stage, such an input stage could include a PMOS input stage. Further, the differential amplifier stage may include a current source or the like between the common source connections of differential pair N73/N74 and ground. The circuit set forth in FIG. 7A can comply with the high speed transceiver logic (HSTL) standard set forth in EIA/JEDEC Standard JESD8-6.
On-die-termination (ODT) can reduce component cost and board size. Unfortunately the termination impedance in ODT arrangements can vary. This can be due to uncontrollable process variation, or the like. Such variation in ODT impedance can translate into corresponding variations in a signal common mode voltage. As but one very particular example, in an HSTL case, a signal common mode voltage variation can be as large ±65 mV with respect to a reference voltage, as compared to actual signal swing, which can be 300 mV. More particularly, signal common mode variation can be as large as ±40 mV with a ±25 mV variation in reference voltage, for an overall variation of ±65 mV. This will be referred herein as signal common mode variation or signal offset from reference voltage.
Signal common mode voltage variations can lead to undesirable jitter in signal reception response. More particularly, some input/output signaling conventions can impose relatively slow signal rise rates (e.g., 1V/ns) at a system level. Such low signal rise rates can contribute to high jitter (e.g., 130 ps) as a signal sampling point varies with respect to the varying signal common mode voltage, as shown in FIG. 7B. Consequently, this can distort the pulse width/duty cycle of an output signal provided by the input circuit, translating into overall jitter and reduction in overall timing budget.
The above drawbacks to a conventional approach like that of FIG. 7A are shown in more detail in a timing diagram of FIG. 7B.
FIG. 7B is a timing diagram that shows a reference voltage REF with respect to three input signals (IN0 to IN2) having increasingly larger common mode voltages. As is shown by the timing diagram, the point at which a logic high is detected (e.g., point in time at which the signal level exceeds REF or falls below REF) can vary considerably according to signal common mode voltage. This can lead to pulse width distortion of an output signal generated by an input circuit.
While the HSTL standard has been described as one type of signaling that may utilize single ended input configuration, other known signaling conventions are known that may include single ended signaling. Such other signaling conventions may suffer from some or all of the above drawbacks. Example of other signaling conventions include, but are not limited to: low voltage positive emitter coupled logic (LVPECL), low voltage differential logic (LVDS), current mode logic (CML), and gunning transistor logic (GTL), to name just a few.
In light of the above, it would be desirable to arrive at a single ended referential input arrangement that can be less susceptible to signal common mode voltage variation than the conventional approaches described above.